Phase-lock loops are widely used in integrated circuit devices for communication applications. In such integrated circuits, a phase-lock loop generates an output clock signal based on a reference clock signal and generates a feedback clock signal based on the output clock signal. Further, the phase-lock loop locks a phase of the feedback clock signal with a phase of the reference clock signal. When the phase of the feedback clock signal is locked with the phase of the reference clock signal, the phase-lock loop is considered to be locked. Moreover, the frequency of the output clock signal is constant when the phase-lock loop is locked.
Some communication applications require the phase-lock loop to maintain the frequency of the output clock signal constant if the reference clock signal becomes unavailable when the phase-lock loop is locked. Maintaining the frequency of the output clock signal constant when the reference clock becomes unavailable is often referred to as a holdover of the phase-lock loop. One technique for performing a holdover of a phase-lock loop involves setting an output of a charge-pump of the phase-lock loop into a high-impedance state so that a capacitor in a loop filter of the phase-lock loop maintains a constant loop filter voltage. In this technique, a voltage-controlled oscillator of the phase-lock loop temporarily maintains the frequency of the output clock signal constant when the output of the charge pump is in the high-impedance state. Because the capacitor in the loop filter has a leakage current, however, the loop filter voltage eventually decays causing the frequency of the output clock signal to drift away from the constant frequency.
In light of the above, a need exists for an improved system and method for performing a holdover of a phase-lock loop. A further need exists for maintaining the frequency of an output clock signal of a phase-lock loop constant during a holdover of the phase-lock loop.